PEX8603, pci express gen 2 switch, 3 lanes, 3 ports ? plx technology, www.plxtech.com page 1 of 3 8/17/2011 , version 1.1 highlights ? PEX8603 general features o 3 - lane, 3 - port pcie gen2 switch ? integrate 5.0 gt/s serdes o 10 x 10mm 2 , 13 6 - pin qfn package o typical power: 0. 7 watts ? PEX8603 key featu res o standards compliant ? pci express base specification, r2. 1 (backwards compatible w/ pcie 1.0a/1.1) ? pci power management spe c, r1.2 ? microsoft windows 7 compliant ? dynamic serdes s peed control o high performance ? non - blocking switch fabr ic ? full line rate on all ports ? packet cut - thru with 250ns max packet l atency (x1 to x1) ? 256b max payload siz e o f lexible configuration ? ports configurable as x1, x2 ? regist ers configurable with strapping p ins, eeprom, i 2 c , or host software ? reference clock buffered output signals for down stream ports ? lane and polarity reversal ? compatible with pcie 1.0a pm o q uality of service (qos) ? eight traffic classes p er port ? round - robin source p ort arbitration ? relaxed pci ordering o re l iability, availability, serviceability ? visionpak ? ? per port performance monitoring ? per port payload & header counters ? s erdes eye capture ? error injection and loopback ? all ports hot plug capable thru i 2 c (hot - plug controller on every port) ? data path parity ? memory (ram) error correction signals ? inta# and fatal_err# ? advanced error reporting ? port status bits and gpio ava ilable ? per port error diagnostics ? jtag ac/dc boundary scan o power management ? wake#, beacon, vaux support the expresslane ? PEX8603 device offers pci express switching capability enabling users to add scalable high bandwidth non - blocking interconnection to a wide variety of applications including control plane applications, consumer applications and embedded systems . the PEX8603 is wel l suited for fan - out and peer -to - peer applications . low packet latency & high performance the PEX8603 architecture supports packet cut - thru with a maximum latency of 250ns in x1 to x1 configuration . this, combined with low power consumption and non - blocking internal switch architecture, provides full line rate on all ports for low - power applications such as consumer and embedded . the low latency enables applications to achieve high throughput and pe rformance. in addition to low latency, the device supports a max payload size of 256 bytes . data integrity the PEX8603 provides end -to - end crc protection (ecrc) and poison bit support to enable designs that require guaranteed error - free packets . plx also supports data path parity and memory (ram ) error correction as packets pass through the switch. power management and reference clock buffers the PEX8603 supports the following power management states: l0, l0s, l1, l2/l3 ready, l2 and l3. moreover, the PEX8603 supports vaux along with the external signal wake# and the in - band beacon for the pcie endpoints to use to inform the system host to exit the low power savings mode. the pex 8603 supports two pairs of buffered, 100 mhz hcsl output clocks, one pair for each downstream port of the switch. each clock output pair can be disabled by software or serial eeprom when not in use , for additional power savings. this feature greatly reduces system bom cost by eliminating the need for extra clock buffers on th e pcb. interoperability the PEX8603 is designed to be fully compliant with the pci express base specification r2. 1 and is backwards compatible to pci express base specification r1.1 and r1.0a. additionally each port supports auto - negotiation and polarity reversal . furthermore, the PEX8603 is designed for microsoft windows 7 compliance. all plx switches undergo thorough interoperability testing in plx?s interoperability lab and compliance testing at the pci - sig plug - fest to ensure compatibility wit h pci express devices in the market. device operation configuration flexibility the PEX8603 provides several ways to configure its operations. the device can be configured through strapping pins, i2c interface, cpu configuration cycles and/or an optiona l serial eeprom. this allows for easy debug during the development phase and functional monitoring during the operation phase .
PEX8603, pci express gen 2 switch, 3 lanes, 3 ports ? plx technology, www.plxtech.com page 2 of 3 8/17/2011 , version 1.1 flexible port configurations the PEX8603 flexible architecture supports a number of port configurations as required by the target applications as shown in figure 1 below. figure 1. port configurations serdes power and signal management the PEX8603 provides low power capability that is fully compliant with the pci express power management specification. in addition, the serdes physical links can be turned off when unused for even lower power. the PEX8603 supports software control of the serdes output s to allow optimization of power and signal strength in a system. the plx serdes implementation supports four levels of power ? off, low, typical, and high. the serdes block also supports loop - back modes and advanced reporting of error conditions , which en ables efficient debug and management of the entire system. port arbitration and qos the PEX8603 switch supports hardware fixed round - robin ingress port arbitration. the PEX8603 also supports eight traffic classes (tcs) as defined in the pcie specificatio n . applications suitable for fan - out, consumer, control plane applications, and embedded systems , PEX8603 is suited for a wide variety of form factors and applications. dual - band wireless adapter the PEX8603 switch, with its small package and low power can be used in consumer applications such as a dual - band wireless adapter. figure 2. dual - band wireless adapter with wake#/beacon support integrated in the switch, the PEX8603 is well suited for low power consumer applications such as that described in figure 2 of a dual - band wireless adapter. modem set - top box with its small footprint, the PEX8603 is ideal for consumer applications. figure 3 shows a high level diagram for a modem set - top box. the PEX8603 provides connectivity to a wifi controller for immediate use as well as future expansion. figure 3. modem set - top box block diagram fan- out the PEX8603 can be used in as a fan - out switch to provide additional x1ports. the PEX8603 serdes can function at 2.5gt/s or 5 figure 4. fan - out bandwidth bridge there are three pcie lanes available in the PEX8603 . each one can represent an individual port or alternatively two can be joined to form a x2 port. a x2 port can provide double the bandwidth of a x1 port when all lanes are operating at the same data rates (all at 2.5gt/s or 5.0gt/s). in some instances, th e need to match the bandwidth between devices running at different data rates (2.5gt/s vs 5.0gt/s) is required to sustain the performance of the faster device. figure 5 provides an pex 8603 x1 x1 x1 pex 8603 x2 x1 x1 x1 .. pex 8603 pch cpu 2.5gt/s; 5.0gt/s gen1 x1
pex 8603, pci express gen 2 switch, 3 lanes, 3 ports ? plx technology, www.plxtech.com page 3 of 3 8/17/2011 , version 1.1 example where the PEX8603 is configured as x2, x1. in this example, the x2 link is running at the lower data rate (2.5gt/s) while a single x1 port is running at the higher data rate (5.0 gt/s). in this usage model, the PEX8603 acts as a bridge between gen 1 and gen 2 devices allowing the faster device to operate at it s full bandw idth capabilities. figure 5. gen 1 to gen 2 bandwidth bridge software usage model from a system model viewpoint, each pci express port is a virtual pci to pci bridge device and has its own set of pci express configuration registers. it is through the upstream port that the bios or host can configure the other ports using standard pci en umeration. the virtual pci - to - pci bridges within the PEX8603 are compliant to the pci and pci express system models. the configuration space registers (csrs) in a virtual primary/secondary pci - to - pci bridge are accessible by type 0 configuration cycles thr ough the virtual primary bus interface (matching bus number, device number, and function number). interrupt sources/events the PEX8603 supports the intx interrupt message type (compatible with pci 2.3 interrupt signals) or message signaled interrupts (m si) when enabled. interrupts/messages are generated by PEX8603 for hot - plug events, doorbell interrupts, baseline error reporting, and advanced error reporting. development tools plx offers hardware and software tools to enable rapid customer design act ivity. these tools consist of a hardware module ( PEX8603 rdk), hardware documentation (available at www.plxtech.com ), and a software development kit (also available at www.plxtech.com ) . expresslane PEX8603 rdk the PEX8603 rdk is a hardware module containing the PEX8603 which plugs right into your system. the PEX8603 rdk can be used to test and validate customer software, or used as an evaluation vehicle for PEX8603 fea tures and benefits. the PEX8603 rdk provides everything that a user needs to get their hardware and software development started. figure 6. PEX8603 rapid development kit software development kit (sdk) plx?s software development kit is available for download at www.plxtech.com/sdk . the software development kit includes drivers, source code, and gui interfaces to aid in configuring and debugging the PEX8603 . both performance pak and vision pak are supported by plx?s rdk and sdk, the industry?s most advanced hardware - and software - development kits. product ordering information part number description PEX8603 - aa50ni g 3 lane, 3 port pci express gen 2.0 switch, pb - free (10x10mm 2 PEX8603 - aa rdk aqfn) pex 8603 rapid development kit + cm108 (one x1 upstream port, two x1 downstream ports) pex 8603 - aa - 2u1d rdk pex 8603 rapid development kit + cm107 (one x2 upstream port, one x1 downstream port) plx technology, inc. all rights reserved. plx, the plx lo go, expresslane, read pacing, dual cast , performancepak and visionpak are trademarks of plx technology, inc. all other product names that appear in this material are for identification purposes only and are acknowle dged to be trademarks or registered trademarks of their respective companies. information supplied by plx is believed to be accurate and reliable, but plx assumes no responsibility for any errors that may appear in this material. plx reserves the right, wi thout notice, to make changes in product design or specification. visit www.plxtech.com for more information. pex8518 eeprom dip switch for cfg. jtag header refclk x4 perst# p ort 2 - x4 manual reset 1 2 v -t o - 1 v n o n - i s o c o n v e r t e r (upstream port) lane status leds p ort 1 - x4 reset ckt. i2c pex 8518 pex 8603
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